The present invention is related to data storage circuits, and more particularly to Sub-threshold memory devices.
A number of different memory devices have been developed. FIG. 1 shows a typical memory array 100 including a number of bit cells 110 that are each capable of storing one bit of information. Bit cells 110 are read and written after being addressed using a row decoder 120 and a column decoder 130. Row decoder 120 drives a number of word lines 121 and column decoder 130 drives a number of bit lines 131. FIG. 2 provides a detailed drawing of exemplary bit cell 110. Bit cell 110 is driven by word line 121, and the bit line and an inverted version of the bit line (bit_line_b) provide an indication of the data stored in bit cell 110. Bit cell 110 includes two NMOS transistors 210, 220 and two inverters 230, 240. The bit line is electrically coupled to the drain of NMOS transistor 220, and the inverted bit line is electrically coupled to the source of NMOS transistor 210. The drain of NMOS transistor 210 is electrically coupled to the source of NMOS transistor 220 via inverter 230 and inverter 240. Word line 121 is electrically coupled to the gate of transistor 210 and the gate of transistor 220.
In operation, reading and writing bit cell 110 is accomplished using the same port including word line 121 and the two bit lines. Bit cell 110 can be made very small due to the small number of wires accessing the cell. During a read operation, when word line 121 is asserted high, one of the bit line and the inverted bit line is asserted high, and the other is asserted low. These bit line values may each be provided to a sense circuit capable of sensing the value on the particular bit line and providing an output reflecting the detected value. Similar to a read operation, during a write operation one of the bit line or the inverted bit line is asserted high, and the other is asserted low. In this condition, asserting word line 121 high causes the value on the bit lines to be stored in bit cell 110.
The aforementioned approach allows for high density devices due to the very small number of access wires feeding bit cell 110. However, a substantial voltage differential between the power supply and the ground must be maintained in order to assure accurate operation. Further, the operation of bit cell 110 may be substantially impacted by process and environmental variations.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and devices for implementing memory and register devices.